The present invention relates to a semiconductor integrated-circuit device and a method for speeding up CMOS circuit operation, and more particularly to a technology advantageously used for speeding up the operation of semiconductor integrated-circuit devices comprising CMOS circuits.
In Japanese Patent Laid-open No. 11-195976, the present applicant has already proposed a MOSFET-constructed semiconductor integrated-circuit device in which there is attained a preferred harmony between operating speed and increases in power consumption due to leakage currents. According to the above-mentioned publication, among the plurality of signal paths in the semiconductor integrated-circuit device, a signal path having a margin for delay with which a signal is transferred along the signal path is constituted by MOSFETs with high threshold voltage. Conversely, a path not having a margin for delay is constituted by low-threshold-voltage MOSFETs which, although large in sub-threshold leakage current, operate at high speed. Means for achieving a high threshold voltage and a low threshold voltage in the MOSFETs as mentioned above can be obtained by changing the density of the impurities under the gate oxide film of the semiconductor substrate, by changing the thickness of the gate oxide film, by changing the substrate bias voltage applied to a well region, by changing the gate length, and by combining these methods. Also, a semiconductor integrated-circuit device that uses high-withstand-voltage MOSFETs and high-threshold-voltage MOSFETs in its input/output circuits is described in Japanese Patent Laid-open No. 2001-015704.